View M36LLR8760B1_594739.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

M36LLR8760T1, M36LLR8760D1 M36LLR8760M1, M36LLR8760B1
256 + 128 Mbit (Multiple Bank, Multi-Level, Burst) Flash Memory 64 Mbit (Burst) PSRAM, 1.8V Supply, Multi-Chip Package
TARGET SPECIFICATION
FEATURES SUMMARY

MULTI-CHIP PACKAGE - 1 die of 256 Mbit (16Mb x16, Multiple Bank, Multi-level, Burst) Flash Memory - 1 die of 128 Mbit (8Mb x16, Multiple Bank, Multi-Level, Burst) Flash Memory - 1 die of 64 Mbit (4Mb x16) Pseudo SRAM SUPPLY VOLTAGE - VDDF1 = VDDF2 = VCCP = VDDQF = 1.7 to 1.95V - VPPF = 9V for fast program (12V tolerant) ELECTRONIC SIGNATURE - Manufacturer Code: 20h - Top Configuration (Top + Top) M36LLR8760T1: 880Dh + 88C4h - Mixed Configuration (Bottom + Top) M36LLR8760D1: 880Eh + 88C4h - Mixed Configuration (Top + Bottom) M36LLR8760M1: 880Dh + 88C5h - Bottom Configuration (Bottom + Bottom) M36LLR8760B1: 880Eh + 88C5h PACKAGE - Compliant with Lead-Free Soldering Processes - Lead-Free Versions
Figure 1. Package
FBGA
LFBGA88 (ZAQ) 8 x 10mm

FLASH MEMORIES

SYNCHRONOUS / ASYNCHRONOUS READ - Synchronous Burst Read mode: 54MHz - Asynchronous Page Read mode - Random Access: 85ns SYNCHRONOUS BURST READ SUSPEND PROGRAMMING TIME - 10s typical Word program time using Buffer Enhanced Factory Program command MEMORY ORGANIZATION - Multiple Bank Memory Array: 16 Mbit Banks for the 256 Mbit Memory 8 Mbit Banks for the 128 Mbit Memory - Parameter Blocks (at Top or Bottom)
COMMON FLASH INTERFACE (CFI) 100,000 PROGRAM/ERASE CYCLES per BLOCK DUAL OPERATIONS - program/erase in one Bank while read in others - No delay between read and write operations SECURITY - 64 bit unique device number - 2112 bit user programmable OTP Cells BLOCK LOCKING - All blocks locked at power-up - Any combination of blocks can be locked with zero latency - WPF for Block Lock-Down - Absolute Write Protection with VPPF = VSS
PSRAM

ACCESS TIME: 70ns ASYNCHRONOUS PAGE READ - Page Size: 16 words - Subsequent read within page: 20ns LOW POWER FEATURES - Temperature Compensated Refresh (TCR) - Partial Array Refresh (PAR) - Deep Power-Down (DPD) Mode SYNCHRONOUS BURST READ/WRITE
1/19
July 2005
This is preliminary information on a new product forseen to be developed. Details are subject to change without notice.
M36LLR8760T1, M36LLR8760D1, M36LLR8760M1, M36LLR8760B1
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 FLASH MEMORIES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Figure 1. Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 PSRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Figure 3. LFBGA Connections (Top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Address Inputs (A0-A23). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Data Input/Output (DQ0-DQ15). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Latch Enable (L). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Clock (K).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Wait (WAIT). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Flash Chip Enable Inputs (EF1, EF2).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Flash Output Enable Inputs (GF1, GF2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Flash Write Enable (WF).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Flash Write Protect (WPF). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Flash Reset (RPF). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 PSRAM Chip Enable input (EP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 PSRAM Write Enable (WP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 PSRAM Output Enable (GP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 PSRAM Upper Byte Enable (UBP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 PSRAM Lower Byte Enable (LBP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 PSRAM Configuration Register Enable (CRP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 VDDF1/VDDF2 Supply Voltages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 VCCP Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 VDDQF Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 VPPF Program Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 VSS Ground.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 4. Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Table 2. Main Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Table 3. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Table 4. Operating and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 5. AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2/19
M36LLR8760T1, M36LLR8760D1, M36LLR8760M1, M36LLR8760B1
Figure 6. Table 5. Table 6. Table 7. Table 8. Table 9. AC Measurement Load Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Device Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Flash 1 DC Characteristics - Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Flash 2 DC Characteristics - Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Flash 1 and Flash 2 DC Characteristics - Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 PSRAM DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 7. LFBGA88 8x10mm, 8x10 ball array - 0.8mm pitch, Bottom View Package Outline . . . . 15 Table 10. Stacked LFBGA88 8x10mm - 8x10 active ball array, 0.8mm pitch, Package Data. . . . . 15 PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 11. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Table 12. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3/19
M36LLR8760T1, M36LLR8760D1, M36LLR8760M1, M36LLR8760B1
SUMMARY DESCRIPTION
The M36LLR8760T1, M36LLR8760D1, M36LLR8760M1 and M36LLR8760B1 combine three memory devices in a Multi-Chip Package: a 256-Mbit, Multiple Bank Flash memory, the M30L0R8000(T/B)0 (Flash 1) a 128-Mbit, Multiple Bank Flash memory, the M58LR128GT/B (Flash 2) a 64-Mbit PseudoSRAM, the M69KB096AA. For detailed information on how to use the memory components, refer to the M30L0R8000(T/B)0, M58LR128GT/B and M69KB096AA datasheets which are available from your local STMicroelectronics distributor and should be read in conjunction with the M36LLR8760x1 datasheet. What differs between the M36LLR8760T1, M36LLR8760D1 and M36LLR8760B1 is the configuration of the two Flash memories: in the M36LLR8760T1, Flash 1 and Flash 2 both have a Top Configuration (Parameter Blocks located at the top of the address space). in the M36LLR8760D1, Flash 1 has a Bottom Configuration (Parameter Blocks at the bottom of the address space) and Flash 2 has a Top Configuration. In the M36LLR8760M1, Flash 1 has a Top Configuration and Flash 2 has a Bottom Configuration. In the M36LLR8760B1, both Flash 1 and Flash 2 have a Bottom Configuration. Recommended operating conditions do not allow more than one memory to be active at the same time. The memories are offered in a Stacked LFBGA88 (8 x 10mm, 8x10 ball array, 0.8mm pitch) package. In addition to the standard version, the package is also available in Lead-free version, in compliance with JEDEC Std J-STD-020B, the ST ECOPACK 7191395 Specification, and the RoHS (Restriction of Hazardous Substances) directive. All packages are compliant with Lead-free soldering processes. The memory is supplied with all the bits erased (set to `1').
4/19
M36LLR8760T1, M36LLR8760D1, M36LLR8760M1, M36LLR8760B1
Figure 2. Logic Diagram
VDDQF VPPF VCCP 16 DQ0-DQ15
Table 1. Signal Names
A0-A23(1) Address Inputs
VDDF1 VDDF2 24 A0-A23
DQ0-DQ15 Common Data Input/Output L K WAIT VDDF1 Common Flash and PSRAM Latch Enable Input Common Flash and PSRAM Burst Clock Wait Data in Burst Mode for both Flash memories and PSRAM Flash 1 Power Supply Flash 2 Power Supply Common Flash Supply for I/O Buffers Common Flash Optional Supply Voltage for Fast Program & Erase Common, Ground PSRAM Power Supply Not Connected Internally Do Not Use as Internally Connected
EF1 GF1 EF2 GF2 WF RPF WPF L K EP GP WP CRP UBP LBP M36LLR8760T1 M36LLR8760D1 M36LLR8760M1 M36LLR8760B1
WAIT
VDDF2 VDDQF VPPF VSS VCCP NC DU
Flash Memory Signals EF1 GF1 Flash 1 Chip Enable Input Flash 1 Output Enable Input Flash 2 Chip Enable Input Flash 2 Output Enable Input Common Flash Memory Write Enable Input Common Flash Memory Reset input Common Flash Memory Write Protect Input
VSS
AI10908b
EF2 GF2 WF RPF WPF
PSRAM Signals EP GP WP CRP UBP LBP Chip Enable Input Output Enable Input Write Enable Input Configuration Register Enable Input Upper Byte Enable Input Lower Byte Enable Input
Note: 1. A22 is an Address Input for the two Flash memories only. A23 is for the 256Mb Flash memory component only.
5/19
M36LLR8760T1, M36LLR8760D1, M36LLR8760M1, M36LLR8760B1
Figure 3. LFBGA Connections (Top view through package)
A
DU
DU
DU
DU
B
A4
A18
A19
VSS
VDDF1
VDDF2
A21
A11
C
A5
LBP
A23
VSS
NC
K
A22
A12
D
A3
A17
NC
VPPF
WP
EP
A9
A13
E
A2
A7
NC
WPF
L
A20
A10
A15
F
A1
A6
UBP
RPF
WF
A8
A14
A16
G
A0
DQ8
DQ2
DQ10
DQ5
DQ13
WAIT
EF2
H
GP
DQ0
DQ1
DQ3
DQ12
DQ14
DQ7
GF2
J
NC
GF1
DQ9
DQ11
DQ4
DQ6
DQ15
VDDQF
K
EF1
DU
DU
NC
VCCP
VDDF2
VDDQF
CRP
L
VSS
VSS
VDDQF
VDDF1
VSS
VSS
VSS
VSS
M
DU
DU
DU
DU
AI10503b
Note: A22 is an Address Input for the two Flash memories only. A23 is for the 256Mb Flash memory component only.
6/19
M36LLR8760T1, M36LLR8760D1, M36LLR8760M1, M36LLR8760B1
SIGNAL DESCRIPTIONS
See Figure 2., Logic Diagram and Table 1., Signal Names, for a brief overview of the signals connected to this device. Address Inputs (A0-A23). Addresses A0-A21 are common inputs for the Flash memory and PSRAM components. A22 is common to the two Flash memory components whereas A23 is an address input for the 256 Mbit Flash memory component only. The Address Inputs select the cells in the memory array to access during Bus Read operations. During Bus Write operations they control the commands sent to the Command Interface of the internal state machine. The Flash memories are accessed through the Chip Enable signal (EF) and through the Write Enable signal (W F), while the PSRAM is accessed through the Chip Enable signal (EP) and the Write Enable signal (WP). It is not allowed to have EF Low, and EP Low at the same time. Data Input/Output (DQ0-DQ15). The Data I/O output the data stored at the selected address during a Bus Read operation or input a command or the data to be programmed during a Bus Write operation. For the PSRAM component, the upper Byte Data Inputs/Outputs (DQ8-DQ15) carry the data to or from the upper part of the selected address when Upper Byte Enable (UBP) is driven Low. The lower Byte Data Inputs/Outputs (DQ0-DQ7) carry the data to or from the lower part of the selected address when Lower Byte Enable (LBP) is driven Low. When both UBP and LBP are disabled, the Data Inputs/ Outputs are high impedance. Latch Enable (L). The Latch Enable pin is common to the Flash memory and PSRAM components. For details of how the Latch Enable signal behaves, please refer to the datasheets of the respective memory components: M69KB096AA for the PSRAM and M30L0R8000(T/B)0 and M58LR128GT/B for Flash 1 and Flash 2, respectively. Clock (K). The Clock input pin is common to the Flash memory and PSRAM components. For details of how the Clock signal behaves, please refer to the datasheets of the respective memory components: M69KB096AA for the PSRAM and M30L0R8000(T/B)0 and M58LR128GT/B for Flash 1 and Flash 2, respectively. Wait (WAIT). WAIT is an output pin common to the Flash memory and PSRAM components. However the WAIT signal does not behave in the same way for the PSRAM and the Flash memories. For details of how it behaves, please refer to the M69KB096AA datasheet for the PSRAM and to the M30L0R8000T/B0 and M58LR128GT/B datasheets for Flash 1 and Flash 2, respectively. Flash Chip Enable Inputs (EF1, EF2). The Flash Chip Enable inputs activate the control logic, input buffers, decoders and sense amplifiers of the Flash memory component selected (EF1 is used to select Flash 1, EF2 is used to select Flash 2). When Chip Enable is Low, VIL, and Reset is High, VIH, the device is in active mode. When Chip Enable is at VIH the corresponding Flash memory are deselected, the outputs are high impedance and the power consumption is reduced to the standby level. It is not allowed to have EF1 at VIL, EF2 at VIL and EP at VIL at the same time. Only one memory component can be enabled at a time. Flash Output Enable Inputs (GF1, GF2). The Output Enable pins control the data outputs during Flash memory Bus Read operations. Flash Write Enable (WF). The Write Enable controls the Bus Write operation of the Flash memories' Command Interface. The data and address inputs are latched on the rising edge of Chip Enable or Write Enable whichever occurs first. Flash Write Protect (WPF). Write Protect is an input that gives an additional hardware protection for each block. When Write Protect is Low, VIL, Lock-Down is enabled and the protection status of the Locked-Down blocks cannot be changed. When Write Protect is at High, VIH, Lock-Down is disabled and the Locked-Down blocks can be locked or unlocked. (See the Lock Status Table in the M30L0R8000(T/B)0 and M58LR128GT/B datasheets). Flash Reset (RPF). The Reset input provides a hardware reset of the Flash memories. When Reset is at VIL, the memory is in Reset mode: the outputs are high impedance and the current consumption is reduced to the Reset Supply Current IDD2. Refer to Table 6., Flash 1 DC Characteristics - Currents, for the value of IDD2. After Reset all blocks are in the Locked state and the Configuration Register is reset. When Reset is at VIH, the device is in normal operation. Exiting Reset mode the device enters Asynchronous Read mode, but
7/19
M36LLR8760T1, M36LLR8760D1, M36LLR8760M1, M36LLR8760B1
a negative transition of Chip Enable or Latch Enable is required to ensure valid data outputs. The Reset pin can be interfaced with 3V logic without any additional circuitry. It can be tied to VRPH (refer to Table 8., Flash 1 and Flash 2 DC Characteristics - Voltages). PSRAM Chip Enable input (EP). The Chip Enable input activates the PSRAM when driven Low (asserted). When deasserted (VIH), the device is disabled, and goes automatically in low-power Standby mode or Deep Power-down mode. PSRAM Write Enable (WP). Write Enable, WP, controls the Bus Write operation of the PSRAM. When asserted (VIL), the device is in Write mode and Write operations can be performed either to the configuration registers or to the memory array. Enable, PSRAM Output Enable (GP). Output GP, provides a high speed tri-state control, allowing fast read/write cycles to be achieved with the common I/O data bus. PSRAM Upper Byte Enable (UB P). The Upper Byte En-able, UBP, gates the data on the Upper Byte Data Inputs/Outputs (DQ8-DQ15) to or from the upper part of the selected address during a Write or Read operation. PSRAM Lower Byte Enable (LBP). The Lower Byte Enable, LBP, gates the data on the Lower Byte Data Inputs/Outputs (DQ0-DQ7) to or from the lower part of the selected address during a Write or Read operation. If both LBP and UBP are disabled (High) during an operation, the device will disable the data bus from receiving or transmitting data. Although the device will seem to be deselected, it remains in an active mode as long as EP remains Low. PSRAM Configuration Register Enable (CR P). When this signal is driven High, VIH, Write operations load either the value of the Refresh Configuration Register (RCR) or the Bus configuration register (BCR). and VDDF1/VDDF2 Supply Voltages. VDDF1 VDDF2 provide the power supply to the internal cores of Flash 1 and Flash 2, respectively. It is the main power supply for all Flash memory operations (Read, Program and Erase). VCCP Supply Voltage. VCCP provides the power supply to the internal core of the PSRAM device. It is the main power supply for all PSRAM operations. VDDQF Supply Voltage. VDDQF provides the power supply for the Flash memory. This allows all Outputs to be powered independently of the Flash memory and SRAM core power supplies, VDDF and VCCP. VPPF Program Supply Voltage. VPPF is both a control input and a power supply pin for the Flash memories. The two functions are selected by the voltage range applied to the pin. If VPPF is kept in a low voltage range (0V to VDDQF) VPPF is seen as a control input. In this case a voltage lower than VPPLK gives an absolute protection against Program or Erase, while VPPF > VPP1 enables these functions (see Tables 6 and 8, DC Characteristics for the relevant values). VPPF is only sampled at the beginning of a Program or Erase; a change in its value after the operation has started does not have any effect and Program or Erase operations continue. If VPPF is in the range of VPPH it acts as a power supply pin. In this condition VPPF must be stable until the Program/Erase algorithm is completed. VSS Ground. VSS is the common ground reference for all voltage measurements in the Flash (core and I/O Buffers) and PSRAM chips. It must be connected to the system ground. Note: Each Flash memory device in a system should have their supply voltage (VDDF) and the program supply voltage VPPF decoupled with a 0.1F ceramic capacitor close to the pin (high frequency, inherently low inductance capacitors should be as close as possible to the package). See Figure 6., AC Measurement Load Circuit. The PCB track widths should be sufficient to carry the required VPPF program and erase currents.
8/19
M36LLR8760T1, M36LLR8760D1, M36LLR8760M1, M36LLR8760B1
FUNCTIONAL DESCRIPTION
The PSRAM and Flash memory components have separate power supplies but share the same grounds. They are distinguished by three Chip Enable inputs: EF1 and EF2 for Flash 1 and Flash 2, respectively, and EP for the PSRAM. Recommended operating conditions do not allow more than one device to be active at a time. The Figure 4. Functional Block Diagram
VDDF1
most common example is simultaneous read operations on one of the Flash memories and the PSRAM which would result in a data bus contention. Therefore it is recommended to put the other devices in the high impedance state when reading the selected device.
A23 EF1 GF1 Flash 1 256 Mbit Flash Memory
A22 RPF WPF WF A0-A21 EF2 GF2 L K Flash 2 DQ0-DQ15 128 Mbit Flash Memory WAIT VDDF2 VPPF VDDQF
VCCP
VSS
EP GP WP CRP UBP LBP
AI10909b
64 Mbit PSRAM
9/19
M36LLR8760T1, M36LLR8760D1, M36LLR8760M1, M36LLR8760B1
Table 2. Main Operating Modes
Operation Flash Read Flash Write Flash Address Latch Flash Output Disable Flash Standby Flash Reset PSRAM Read PSRAM Write PSRAM Write Configuration Register PSRAM Standby PSRAM Deep Power-Down
Note: 1. 2. 3. 4.
EF(5) GF(5) VIL VIL VIL VIL VIH X VIL VIH X VIH X X
WF
VIH VIL VIH VIH X X
LF VIL(2) VIL(2) VIL X X X
RPF VIH VIH VIH VIH VIH VIL
WAITF(4)
EP
CRP
GP
WP
LBP,UBP
DQ15-DQ0 Flash Data Out
PSRAM must be disabled. Only one Flash memory can be enabled at a time.
Flash Data In Flash Data Out or Hi-Z (3) Hi-Z Hi-Z Hi-Z
Hi-Z Hi-Z
Any PSRAM mode is allowed. Both Flash memories must be disabled.
VIL Both Flash memories must be disabled VIL VIL
VIL VIL VIH
VIL X VIH
VIH VIL VIL
VIL VIL X
PSRAM data out PSRAM data in PSRAM data in
Any Flash memory mode is allowed. Only one Flash memory can be enabled at a time
VIH VIH
VIL X
X X
X X
X X
Hi-Z Hi-Z
X = Don't care. LF can be tied to VIH if the valid address has been previously latched. Depends on GF. WAIT signal polarity is configured using the Set Configuration Register command. See the M30L0R8000(T/B)0 and M30L0R8000(T/B)0 datasheets for details. 5. EF is either EF1 or EF2, and GF is either GF1 or GF2 according to the Flash memory enabled. Only one Flash memory can be enabled at a time.
10/19
M36LLR8760T1, M36LLR8760D1, M36LLR8760M1, M36LLR8760B1
MAXIMUM RATING
Stressing the device above the rating listed in the Absolute Maximum Ratings table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not imTable 3. Absolute Maximum Ratings
Value Symbol TA TBIAS TSTG TLEAD VIO VDDF1, VDDF2, VDDQF, VCCP VPPF IO tVPPFH Parameter Min Ambient Operating Temperature Temperature Under Bias Storage Temperature Lead Temperature During Soldering Input or Output Voltage Core and Input/Output Supply Voltages Flash Program Voltage Output Short Circuit Current Time for VPPF at VPPFH -0.5 -0.2 -0.2 -25 -25 -65 Max 85 85 125
(1)
plied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents.
Unit C C C C V V V mA hours
3.6 2.45 12.6 100 100
Note: 1. Compliant with the JEDEC Std J-STD-020B (for small body, Sn-Pb or Pb assembly), the ST ECOPACK (R) 7191395 specification, and the European directive on Restrictions on Hazardous Substances (RoHS) 2002/95/EU.
11/19
M36LLR8760T1, M36LLR8760D1, M36LLR8760M1, M36LLR8760B1
DC AND AC PARAMETERS
This section summarizes the operating measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC characteristics Tables that follow, are derived from tests performed under the Measurement Conditions summarized in Table 4., Operating and AC Measurement Conditions. Designers should check that the operating conditions in their circuit match the operating conditions when relying on the quoted parameters.
Table 4. Operating and AC Measurement Conditions
Flash Memories Parameter Min VDDF1/VDDF2 Supply Voltages VCCP Supply Voltage VDDQF Supply Voltage 1.7 - 1.7 8.5 -0.4 -25 30 16.7 5 0 to VDDQF VDDQF/2 0 to VDDQF VDDQF/2 Max 1.95 - 1.95 9.5 VDDQF +0.4 85 Min - 1.7 - - - -25 30 16.7 Max - 1.95 - - - 85 V V V V V C pF k ns V V PSRAM Unit
VPPF Supply Voltage (Factory environment) VPPF Supply Voltage (Application environment)
Ambient Operating Temperature Load Capacitance (CL) Output Circuit Resistors (R1, R2) Input Rise and Fall Times Input Pulse Voltages Input and Output Timing Ref. Voltages
Figure 5. AC Measurement I/O Waveform
Figure 6. AC Measurement Load Circuit
VDDQF
VDDQF VDDQF/2 0V DEVICE UNDER TEST 0.1F 0.1F CL R2 VDDF VDDQF R1
AI06161b
CL includes JIG capacitance
AI08364c
Table 5. Device Capacitance
Symbol CIN COUT Parameter Input Capacitance Output Capacitance Test Condition VIN = 0V VOUT = 0V Min Max 14 18 Unit pF pF
Note: Sampled only, not 100% tested.
12/19
M36LLR8760T1, M36LLR8760D1, M36LLR8760M1, M36LLR8760B1
Table 6. Flash 1 DC Characteristics - Currents
Symbol ILI ILO Parameter Input Leakage Current Output Leakage Current Supply Current Asynchronous Read (f=5MHz) IDD1 Test Condition 0V VIN VDDQF 0V VOUT VDDQF EF1 = VIL, GF1 = VIH 4 Word Supply Current Synchronous Read (f=54MHz) 8 Word 16 Word Continuous IDD2 IDD3 IDD4 Supply Current (Reset) Supply Current (Standby) Supply Current (Automatic Standby) Supply Current (Program) IDD5 (1) Supply Current (Erase) VPPF = VDDF1 Program/Erase in one Bank, Asynchronous Read in another Bank Program/Erase in one Bank, Synchronous Read (Continuous f=54MHz) in another Bank EF1 = VDDF1 0.2V VPPF = VPPH VPPF = VDDF1 VPPF = VPPH VPPF = VDDF1 VPPF VDDF1 VPPF VDDF1 10 23 25 40 mA mA VPPF = VDDF1 VPPF = VPPH 10 8 25 20 mA mA RPF = VSS 0.2V EF1 = VDDF1 0.2V EF1 = VIL, GF1 = VIH VPPF = VPPH 13 16 18 23 25 50 50 50 8 Typ Max 1 1 15 18 20 25 27 110 110 110 20 Unit A A mA mA mA mA mA A A A mA
Supply Current IDD6 (1,2) (Dual Operations)
35
52
mA
IDD7(1)
Supply Current Program/ Erase Suspended (Standby) VPPF Supply Current (Program)
50 2 0.2 2 0.2 0.2 0.2
110 5 5 5 5 5 5
A mA A mA A A A
IPP1(1) VPPF Supply Current (Erase) IPP2 IPP3(1) VPPF Supply Current (Read) VPPF Supply Current (Standby)
Note: 1. Sampled only, not 100% tested. 2. VDDF1 Dual Operation current is the sum of read and program or erase currents.
13/19
M36LLR8760T1, M36LLR8760D1, M36LLR8760M1, M36LLR8760B1
Table 7. Flash 2 DC Characteristics - Currents
Symbol ILI ILO Parameter Input Leakage Current Output Leakage Current Supply Current Asynchronous Read (f=5MHz) IDD1 Test Condition 0V VIN VDDQF 0V VOUT VDDQF E = VIL, G = VIH 4 Word Supply Current Synchronous Read (f=54MHz) 8 Word 16 Word Continuous IDD2 IDD3 IDD4 Supply Current (Reset) Supply Current (Standby) Supply Current (Automatic Standby) Supply Current (Program) IDD5 (1) Supply Current (Erase) VPP = VDD Program/Erase in one Bank, Asynchronous Read in another Bank Program/Erase in one Bank, Synchronous Read (Continuous f=54MHz) in another Bank E = VDDQF 0.2V K=VSS VPP = VPPH VPP Supply Current (Program) IPP1(1) VPP Supply Current (Erase) IPP2 IPP3(1) VPP Supply Current (Read) VPP Supply Current (Standby) VPP = VDD VPP = VPPH VPP = VDD VPP VDD VPP VDD 10 23 25 40 mA mA VPP = VDD VPP = VPPH 10 8 25 20 mA mA RP = VSS 0.2V E = VDDQF 0.2V K=VSS E = VIL, G = VIH VPP = VPPH 13 16 18 23 25 25 25 25 8 Typ Max 1 1 15 18 20 25 27 70 70 70 20 Unit A A mA mA mA mA mA A A A mA
IDD6
(1,2)
Supply Current (Dual Operations)
35
52
mA
IDD7(1)
Supply Current Program/ Erase Suspended (Standby)
25 2 0.2 2 0.2 0.2 0.2
70 5 5 5 5 5 5
A mA A mA A A A
Note: 1. Sampled only, not 100% tested. 2. VDDF2 Dual Operation current is the sum of read and program or erase currents.
14/19
M36LLR8760T1, M36LLR8760D1, M36LLR8760M1, M36LLR8760B1
Table 8. Flash 1 and Flash 2 DC Characteristics - Voltages
Symbol VIL VIH VOL VOH VPP1 VPPH VPPLK VLKO VRPH Parameter Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage VPPF Program Voltage-Logic VPPF Program Voltage Factory Program or Erase Lockout VDDF1/F2 Lock Voltage RPF pin Extended High Voltage IOL = 100A IOH = -100A Program, Erase Program, Erase VDDQF - 0.1 1.1 8.5 1.8 9.0 3.3 9.5 0.4 1 3.3 Test Condition Min 0 VDDQF - 0.4 Typ Max 0.4 VDDQF + 0.4 0.1 Unit V V V V V V V V V
Table 9. PSRAM DC Characteristics
Symbo l Parameter Test Condition 70ns 70ns VCC =VIH or VIL, E = VIL, IOUT = 0mA 80MHz 66MHz 80MHz 66MHz 80MHz 66MHz VCC = VCCQ or 0V, E = VIH 0V VIN VCC G = VIH or E = VIH VIN = VIH or VIL 1.4 -0.2 IOH = -0.2mA IOL = 0.2mA 0.8VCC
Q
Min.
Typ
Max. 25 15 35 30 18 15 35 30 120 1 1
Uni t mA mA mA mA mA mA mA mA A A A A
Operating Current: Asynchronous Random ICC1 (1) Read/Write ICC1P
(1)
Operating Current: Asynchronous Page Read
Operating Current: ICC2 (1) Initial Access, Burst Read/Write ICC3R(1) Operating Current: Continuous Burst Read
ICC3W(1 Operating Current: Continuous Burst Write ) ISB(2) ILI ILO IZZ VIH VIL VOH VOL VCC Standby Current Input Leakage Current Output Leakage Current Deep-Power Down Current Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage
10 VCCQ + 0.2 0.4
V V V
0.2VCCQ
V
Note: 1. This parameter is specified with the outputs disabled to avoid external loading effects. The user must add the current required to drive the output capacitance expected in the actual system. 2. ISB(Max) values are measured with RCR2 to RCR0 bits set to `000' (full array refresh) and RCR6 to RCR5 bits set to `11' (temperature compensated refresh threshold at +85C). In order to achieve low standby current, all inputs must be driven either to VCCQ or VSS. 3. The Operating Temperature is +25C.
15/19
M36LLR8760T1, M36LLR8760D1, M36LLR8760M1, M36LLR8760B1
PACKAGE MECHANICAL
Figure 7. LFBGA88 8x10mm, 8x10 ball array - 0.8mm pitch, Bottom View Package Outline
D D1
e SE E E2 E1 b BALL "A1" e ddd FE1 FE FD A A1 SD A2
BGA-Z45
Note: Drawing is not to scale.
Table 10. Stacked LFBGA88 8x10mm - 8x10 active ball array, 0.8mm pitch, Package Data
millimeters Symbol Typ A A1 A2 b D D1 ddd E E1 E2 e FD FE SD SE FE1 10.000 7.200 8.800 0.800 1.200 1.400 0.400 0.400 0.600 9.900 - - - - - - - - 1.000 0.350 8.000 5.600 0.300 7.900 - 0.400 8.100 - 0.100 10.100 - - - - - - - - 0.3937 0.2835 0.3465 0.0315 0.0472 0.0551 0.0157 0.0157 0.0236 0.3898 - - - - - - - - 0.200 0.0394 0.0138 0.3150 0.2205 0.0118 0.3110 - 0.0157 0.3189 - 0.0039 0.3976 - - - - - - - - Min Max 1.400 0.0079 Typ Min Max 0.0551 inches
16/19
M36LLR8760T1, M36LLR8760D1, M36LLR8760M1, M36LLR8760B1
PART NUMBERING
Table 11. Ordering Information Scheme
Example: Device Type M36 = Multi-Chip Package (Multiple Flash + RAM) Flash 1 Architecture L = Multi-Level, Multiple Bank, Burst mode Flash 2 Architecture L = Multi-Level, Multiple Bank, Burst mode Operating Voltage R = VDDF = VCCP = VDDQF = 1.7 to 1.95V Flash 1 Density 8 = 256 Mbits Flash 2 Density 7 = 128 Mbits RAM 1 Density 6 = 64 Mbits RAM 0 Density 0 = No Die Parameter Blocks Location T = Top Boot Block Flash B = Bottom Boot Block Flash D = Mixed (Flash 1 Bottom, Flash 2 Top) M = Mixed (Flash 1 Top, Flash 2 Bottom) Product Version 1 = 0.13m Flash technology (2 Chip Enable inputs, one for each Flash memory), 85ns speed; 0.11m PSRAM, 70ns speed, burst mode Package ZAQ = Stacked LFBGA88 8x10mm - 8x10 active ball array, 0.8mm pitch Option Blank = Standard Packing T = Tape & Reel Packing E = Lead-free and RoHS Standard packing F = Lead-free and RoHS Tape & Reel packing M36 L L R8 76 0 T 1 ZAQ T
Devices are shipped from the factory with the memory content bits erased to '1'. For a list of available options (Speed, Package, etc.) or for further information on any aspect of this device, please contact the STMicroelectronics Sales Office nearest to you.
17/19
M36LLR8760T1, M36LLR8760D1, M36LLR8760M1, M36LLR8760B1
REVISION HISTORY
Table 12. Document Revision History
Date 29-Apr-2004 01-Feb-2005 13-July-2005 Version 0.1 0.2 0.3 First Issue Part Number M69KB096A changed to M69KB096AA throughout document. VDDQ changed to VDDQF throughout the document. Table 6., Table 7., Table 8. and Table 9. modified. Revision Details
18/19
M36LLR8760T1, M36LLR8760D1, M36LLR8760M1, M36LLR8760B1
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. ECOPACK is a registered trademark of STMicroelectronics. All other names are the property of their respective owners (c) 2005 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com
19/19

▲Up To Search▲

Price & Availability of M36LLR8760B1

	To Download M36LLR8760B1 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .